EmuCR Feeds
Email Us

EmuCR: Cen64Cen64 Git (2016/07/10) is compiled. Cen64 is a Cycle-Accurate Nintendo 64 Simulator.

Cen64 Git Changelog:
* rsp: Qualify shuffle arrays as static.
* rsp: Fix SQV and SRV (more endianness issues).
* rsp: Fix SP->RDRAM stride bug.
krom spotted this one using his upcoming GB emulator.
* rsp: Fix LRV bug (data shifting problem).
tl;dr: Using LUTs to shift and byteswap all in one x86
instruction is awesome for performance, but makes things
absolutely horrendous to debug.
With this commit, audio mixing on the RSP works properly.
* rsp: Fix LQV bug (related to endianness).
* rsp: Fix LPV bug (more endianness issues).
* rsp: Fix LBV bug (related to endianness).
* rsp: Fix link PC result (12th bit should not get set).
* vr4300: Fix a major TLB bug.
I seriously screwed up the TLB lookup logic so bad that
only the first 8 TLB entries were being probed. Fix that.
This fixes (at least) Paper Mario and Mario Tennis.
* vr4300: Fix a bug in (D) Index Load Tag.
The VALID and DIRTY bits were not being shifted into the
proper positions after reading them from the line states.
* vr4300: Fix a (fairly serious) cache bug.
The action taken for (D) Index_Write_Back_Invalidate was
wrong. As it turns out, the VR4300 manual has an extremely
serious typo in the operation section.
According to the manual, this cache operation should use
the virtual address to index a block (line) in the cache.
If that line is not in the INVALID state, it should be
unconditionally flushed out to memory and the line should
then be invalidated.
The hardware, however, seems to only write back the block
(line) in the event that the line is VALID and DIRTY. It
does, however, invalidate the line regardless of whether
or not the line was DIRTY. That is to say, CLEAN lines get
invalidated as well.
This commit fixes the erroneous behavior.

Download: Cen64 Git (2016/07/10)
Source: Here

Random Related Topic Refresh Related Topic

Random Related Topic Loading...


Post a Comment

Can't post a comment? Try This!