Commodore 64 Emulator v0.8.6.0-alpha is released. A Commodore 64 emulator written in modern C++, built with SDL2 and designed around two priorities:Accuracy-first emulation (with a strong focus on real hardware behavior over “good enough” hacks); Debuggability (integrated monitor, break/watchpoints, and visibility into what the machine is doing). This project is actively under development; expect rough edges and incomplete features.

Commodore 64 Emulator Changelog:
Commodore 64 Emulator v0.8.6.0-alpha
This release includes a large number of accuracy, timing, architecture, debugging, and compatibility improvements since v0.8.4.6-alpha.
The biggest areas of work are:
VIC-II cycle timing and bus behavior
Sprite DMA/fetch accuracy
Bad-line and raster timing
6510 IRQ/NMI timing
SID oscillator, envelope, and filter behavior
System Bus/Memory architecture
Save-state reliability
Cartridge handling
ML Monitor and tracing improvements
This is still an alpha release. Timing-sensitive software may still expose incomplete or inaccurate hardware behavior.
VIC-II
Explicit Phi1 / Phi2 bus timing
The VIC-II bus pipeline has been reworked around explicit Phi1/Phi2 phases.
Added explicit VIC Phi1 and Phi2 execution phases
CPU execution now occurs between VIC Phi1 and Phi2 activity
Added explicit bus phases to sprite fetch timing
Moved graphics accesses to Phi1
Moved DRAM refresh accesses to Phi1
Moved sprite pointer fetches to Phi1
Split sprite data fetches across Phi1/Phi2
Added phase-aware VIC bus ownership
Removed the legacy whole-cycle bus owner model
Added Phi1/Phi2 bus collision tracing
Improved monitor output for bus ownership and fetch timing
Sprite timing
Sprite fetch and DMA timing received a major accuracy pass.
Corrected PAL sprite fetch spacing
Corrected NTSC sprite fetch spacing
Corrected sprite data fetch phases
Improved sprite BA/AEC timing
Made sprite CPU steals Phi2-aware
Improved sprite fetch scheduling
Corrected sprite 7 MCBASE update ordering
Corrected sprite-to-sprite priority behavior
Improved sprite output handling after DMA completion
Bad lines and display state
Bad-line handling has been substantially reworked.
Added explicit c-access runtime state
Improved bad-line creation and cancellation behavior
Improved late bad-line DMA takeover handling
Improved cycle 14 and cycle 58 behavior
Preserved display state across late bad-line transitions
Improved BA/AEC timing during bad-line activity
Preserved matrix fetch indexing during late DMA takeover
Decoupled c-access execution from legacy FetchKind handling
Improved invalid c-access handling
Fixed an idle-display graphics latch regression affecting BC's Quest for Tires
Raster IRQ behavior
Raster interrupt timing and register behavior received another major accuracy pass.
Reworked raster IRQ acknowledgement and retarget handling
Improved RMW handling for raster IRQ register writes
Improved same-line comparator behavior
Improved deferred IRQ reassert handling
Corrected raster 0 IRQ timing
Improved D019/D01A readback semantics
Added VIC data-bus latch behavior for D019/D01A reads
Register timing
Raster events now record actual VIC bus phase
Corrected Phi2 raster-event pixel positioning
Improved D011 timing
Improved D016 timing
Improved D018 timing
Improved mid-raster register write handling
Improved light-pen latch behavior
Legacy renderer cleanup
Removed remaining legacy line-based rendering paths in favor of the active cycle/pixel pipeline.
Removed legacy rendering for:
Standard text
Bitmap
Multicolor bitmap
ECM
generateBackgroundLine()
6510 CPU
IRQ polling and interrupt timing were expanded across a large portion of the CPU micro-op engine.
Improvements include sampled IRQ polling for:
Branches
Implied instructions
Immediate instructions
Stack operations
JSR / RTS / RTI / JMP
Zero-page operations
Indexed operations
Read/modify/write instructions
Indexed-indirect and indirect-indexed instructions
Undocumented NOP variants
Additional improvements:
Improved NMI hijack timing
Improved IRQ/BRK vector hijacking
Added sampled IRQ state to save states
Expanded CPU IRQ tracing
SID
Oscillator
Added model-specific combined waveform handling
Improved triangle/saw/pulse combinations
Improved noise combined-waveform behavior
Modeled noise LFSR collapse behavior
Improved TEST-bit and LFSR reset behavior
Added pulse comparator pipeline delay
Improved silent noise waveform DAC behavior
Envelope
Decoupled envelope timing from audio sample rate
Corrected 15-bit rate-counter wrapping
Improved exponential divider behavior
Improved gate-off release handling
Simplified internal envelope state
Removed obsolete envelope pipeline code
Filter
Improved 6581 resonance mapping
Improved 8580 resonance mapping
Improved 8580 cutoff range
Added 2x filter oversampling
Removed hard clipping from filter state
Reduced redundant filter recalculation
Bus and Memory Architecture
A major internal refactor moved hardware devices away from direct Memory dependencies and onto the system Bus.
Changes include:
Added and expanded the system Bus implementation
Migrated CPU access to the Bus
Migrated VIC memory access to the Bus
Migrated REU DMA access to the Bus
Migrated ML Monitor memory access to the Bus
Migrated cartridge access away from Memory-owned ROM storage
Added dedicated CPU6510Port support
Added save/load state support for CPU6510Port
Removed obsolete Memory read/write and I/O interfaces
Removed legacy device attachments from Memory
The cartridge subsystem now owns its ROM storage directly.
Cartridge Improvements
Hardened cartridge file loading
Added CRT magic validation
Improved initial bank selection
Expanded cartridge bank handling
Fixed 8K cartridge loading into $E000
Added bounds checking to cartridge metadata handling
Improved mapper Bus attachment
Save States
Added rollback when loading a save state fails
Improved state validation
Added raster IRQ state persistence
Added light-pen latch state persistence
Added sampled CPU IRQ state
Added CPU6510Port state support
Improved legacy VIC state handling
Removed legacy VICX v1 state support
ML Monitor and Tracing
Added VIC bus diagnostics
Added CPU PC-range tracing
Expanded CPU IRQ tracing
Expanded VIC raster IRQ tracing
Improved VIC raster event summaries
Improved VIC background debug output
Improved snapshot-based VIC diagnostics
Added phase-aware Phi1/Phi2 bus ownership reporting
Fixed VIC cycle breakpoint state
Improved breakpoint/watchpoint listing
Fixed persistent stream formatting between commands
Improved raster wait-loop detection
Added additional pointer and bounds checks
Video and UI
Improved C64 window sizing and scaling
Improved resize/maximize behavior
Improved startup window sizing
Added Pepto NTSC Sony palette
Added Pepto palette attribution
Improved NTSC color handling
Improved PAL/NTSC palette synchronization
Improved Help menu formatting
Added Getting Started help
Added Keyboard Shortcuts help
Additional Fixes
Improved keyboard modifier/shared-key handling
Fixed 1581 device-number switch behavior
Hardened ROM loading and initialization
Improved VIC live CIA2 bank handling
Corrected PAL bad-line DMA start timing
Improved graphics fetch indexing
Improved character sequencer behavior
Improved sprite debug tracing
Added additional state-load safety checks
Known Status
This release contains substantial internal timing changes, especially in the VIC-II and CPU.
Raster-sensitive games and demos should generally behave more accurately, but additional edge cases are still expected while cycle-exact behavior continues to be refined.
Version: v0.8.6.0-alpha
Changes since: v0.8.4.6-alpha
Assets
3
v0.8.6.0-alpha.zip
sha256:510fe9540c0fd7a6ca1ca5bbdf79f74ec588338fcb1f2184988727e78f990489
5.61 MB
今天 06:54:32
Source code (zip)
今天 06:35:00
Source code (tar.gz)
今天 06:35:00
v0.8.4.6-alpha
v0.8.4.6-alpha
@cbroschard cbroschard released this 08-28 04:55:08
v0.8.4.6-alpha
db15b8f
v0.8.4.6-alpha
This release focuses heavily on VIC-II accuracy, CPU/VIC timing, stability, media handling, and emulator architecture.
A major part of the work over the past two weeks has been moving additional VIC-II behavior away from scanline-level approximations and toward more accurate cycle-based execution.
Highlights
Major VIC-II fetch and graphics pipeline improvements
Fixed significant graphics issues in RoboCop 3
Fixed a graphics regression in Dig Dug
Resolved an Action Biker raster IRQ regression
Improved sprite pointer, DMA, MC/MCBASE, and Y-expansion handling
Improved bad-line and background graphics fetch sequencing
Improved CPU/VIC bus arbitration and interrupt timing
Corrected NMOS 6510 KIL/JAM behavior in the micro-op CPU path
Improved repeated T64/datasette loading
Hardened emulator shutdown against intermittent access violations
Continued save-state compatibility and versioning improvements
Continued SID oscillator/state architecture work
Expanded VIC-II and CPU diagnostics in the built-in monitor
Fixed regression from last release where old palette was loaded during SDL 2 to 3 upgrade
VIC-II Improvements
The VIC-II execution pipeline received substantial timing and architecture work.
Graphics Fetch Pipeline
Background graphics accesses are now handled during the VIC fetch phase rather than being coupled to later rendering activity.
Graphics sequencer advancement now occurs after the appropriate graphics memory access.
This provides more accurate ordering between:
VIC memory accesses
CPU bus availability
graphics sequencing
sprite activity
register changes
Sprite Fetch Timing
Sprite pointer fetching has been moved to the correct fetch-slot timing.
This fixed cases where sprite data could be fetched using stale or incorrect pointer values.
Additional sprite-related work includes:
Sprite DMA sequencing improvements
MC/MCBASE timing improvements
Y-expansion behavior refinements
Sprite pointer fetch timing corrections
Improved sprite state diagnostics
Bad-Line and Register Timing
Additional work was completed around:
Bad-line fetch sequencing
D011 timing
D016 timing
D018 timing
mid-frame VIC register changes
graphics sequencer state
raster event tracking
Compatibility Fixes
RoboCop 3
Fixed major graphics corruption affecting multiple RoboCop 3 screens.
The issue was traced primarily to the ordering of:
background graphics fetches
sprite pointer fetches
graphics sequencer advancement
Sprite pointers are now fetched at the proper VIC fetch-slot boundary and background graphics accesses occur during the appropriate fetch phase.
Dig Dug
Fixed a graphics regression uncovered during VIC-II sequencing changes.
Action Biker
Resolved a raster IRQ comparator regression that caused screen flashing.
Eye of the Beholder
Corrected micro-op CPU behavior when encountering NMOS 6502/6510 KIL/JAM instructions.
Additional graphics compatibility work for this title remains ongoing.
CPU / 6510
Continued improvements to the cycle-accurate micro-op CPU implementation.
Changes include work around:
interrupt recognition timing
RTI behavior
RDY/AEC stalls
CPU/VIC arbitration
stalled instruction fetches
undocumented instructions
KIL/JAM behavior
cycle-level tracing
SID
Continued restructuring of the SID implementation.
Work in this release focuses on keeping behavior that is common to all SID revisions separate from future model-specific behavior.
Additional work was also completed around SID save-state versioning and oscillator state handling.
Save States
Continued improvements to the save state architecture. Any existing save states will not work with this release due to the changes for the SID.
Media / Datasette
Improved repeated T64 loading.
Previously, attaching another T64 while one was already active could overwrite machine state or leave the C64 in an unsuitable state for launching the next program.
Media switching now performs a safer reset/load transition and avoids the emulator freeze encountered during repeated T64 attachment.
Added T64 index selection if there is more than one program to the UI.
Updated UI to show various live statics when using the datasette.
Stability
Improved emulator shutdown and component teardown.
Shutdown now more deliberately disconnects callbacks and cross-component references before components are destroyed.
Areas updated include:
video callbacks
audio shutdown
monitor/debug connections
virtual modem devices
user-port devices
trace managers
cartridge references
chipset references
Run-loop changes also eliminated a reproducible access violation encountered when closing the emulator window introduced in the last release.
Cartridge / Expansion Hardware
Continued cartridge and expansion-device cleanup.
Work includes:
mapper reset-state auditing
continued EasyFlash state review
improved cartridge initialization/reset behavior
moved REU menu from the system menu to the peripheral menu
Monitor / Diagnostics
Expanded the built-in machine-language monitor to assist with cycle-sensitive debugging.
VIC diagnostics now provide increasingly detailed visibility into:
raster and cycle position
VIC registers
color registers
VIC memory banks
screen/character/bitmap locations
sprite DMA state
sprite MC/MCBASE state
sprite pointers
register-write events
raster event summaries
raster IRQ state
CPU tracing and execution diagnostics were also expanded.
Monitor formatting was reviewed to prevent persistent C++ stream settings such as std::setfill() from leaking into later commands, especially help output.
Internal Cleanup
Additional cleanup was completed across the CPU, VIC-II, machine lifecycle, and component interfaces.
This included:
dead-code removal
reducing public API surface
removing obsolete timing paths
separating fetch/render responsibilities
improving component ownership
improving shutdown boundaries
consolidating machine wiring
simplifying future timing work
Known Areas Still Under Development
This remains an alpha release. Active accuracy work continues in areas including:
VIC-II sprite timing
raster IRQ edge cases
PAL/NTSC timing differences
mid-scanline register writes
multicolor graphics edge cases
CPU/VIC arbitration
SID model-specific behavior
cartridge and expansion hardware accuracy
Summary
v0.8.4.6-alpha is primarily an accuracy and stability release.
The most significant improvements are in VIC-II memory-fetch sequencing, sprite timing, CPU/VIC interaction, media handling, save-state robustness, and emulator shutdown stability.

Download: Commodore 64 Emulator v0.8.6.0-alpha
Source: Here